verilog nonblocking assignment

Verilog Blocking & Non-Blocking

Blocking assignment statements are assigned using = and are executed one after the other in a procedural block. However, this will not prevent execution of statments that run in a parallel block.

Note that there are two initial blocks which are executed in parallel when simulation starts. Statements are executed sequentially in each block and both blocks finish at time 0ns. To be more specific, variable a gets assigned first, followed by the display statement which is then followed by all other statements. This is visible in the output where variable b and c are 8'hxx in the first display statement. This is because variable b and c assignments have not been executed yet when the first $display is called.

In the next example, we'll add a few delays into the same set of statements to see how it behaves.

Non-blocking

Non-blocking assignment allows assignments to be scheduled without blocking the execution of following statements and is specified by a symbol. It's interesting to note that the same symbol is used as a relational operator in expressions, and as an assignment operator in the context of a non-blocking assignment. If we take the first example from above, replace all = symobls with a non-blocking assignment operator , we'll see some difference in the output.

See that all the $display statements printed 'h'x . The reason for this behavior lies in the way non-blocking assignments are executed. The RHS of every non-blocking statement of a particular time-step is captured, and moves onto the next statement. The captured RHS value is assigned to the LHS variable only at the end of the time-step.

So, if we break down the execution flow of the above example we'll get something like what's shown below.

Next, let's use the second example and replace all blocking statements into non-blocking.

Once again we can see that the output is different than what we got before.

If we break down the execution flow we'll get something like what's shown below.

Blocking vs. Nonblocking in Verilog

The concept of Blocking vs. Nonblocking signal assignments is a unique one to hardware description languages. The main reason to use either Blocking or Nonblocking assignments is to generate either combinational or sequential logic. In software, all assignments work one at a time. So for example in the C code below:

The second line is only allowed to be executed once the first line is complete. Although you probably didn’t know it, this is an example of a blocking assignment. One assignment blocks the next from executing until it is done. In a hardware description language such as Verilog there is logic that can execute concurrently or at the same time as opposed to one-line-at-a-time and there needs to be a way to tell which logic is which.

<=     Nonblocking Assignment

=      Blocking Assignment

The always block in the Verilog code above uses the Nonblocking Assignment, which means that it will take 3 clock cycles for the value 1 to propagate from r_Test_1 to r_Test_3. Now consider this code:

See the difference? In the always block above, the Blocking Assignment is used. In this example, the value 1 will immediately propagate to r_Test_3 . The Blocking assignment immediately takes the value in the right-hand-side and assigns it to the left hand side. Here’s a good rule of thumb for Verilog:

In Verilog, if you want to create sequential logic use a clocked always block with Nonblocking assignments. If you want to create combinational logic use an always block with Blocking assignments. Try not to mix the two in the same always block.

Nonblocking and Blocking Assignments can be mixed in the same always block. However you must be careful when doing this! It’s actually up to the synthesis tools to determine whether a blocking assignment within a clocked always block will infer a Flip-Flop or not. If it is possible that the signal will be read before being assigned, the tools will infer sequential logic. If not, then the tools will generate combinational logic. For this reason it’s best just to separate your combinational and sequential code as much as possible.

One last point: you should also understand the semantics of Verilog. When talking about Blocking and Nonblocking Assignments we are referring to Assignments that are exclusively used in Procedures (always, initial, task, function). You are only allowed to assign the reg data type in procedures. This is different from a Continuous Assignment . Continuous Assignments are everything that’s not a Procedure, and only allow for updating the wire data type.

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Blocking and Non-blocking Assignment in Verilog

• Assignment is only done in procedural block(always ot initial block)
• Both combintational and sequential circuit can be described.
• Assignment can only possible to reg type irrespect of circuit type

Let's say we want to describe a 4-bit shift register in Verilog. For this, we are required to declare a 3-bit reg type variable.

The output of shift[0] is the input of shift[1], output of shift[1] is input of shift[2], and all have the same clock. Let's complete the description using both assignment operator.

Non-Blocking Assignment

When we do synthesis, it consider non-blocking assignment separately for generating a netlist. If we see register assignment in below Verilog code, all register are different if we consider non-blocking assignment separately. If you do the synthesis, it will generate 3 registers with three input/output interconnects with a positive edge clock interconnect for all register. Based on the Verilog description, all are connected sequentially because shift[0] is assigned d, shift[1] is assigned shift[0], and shift[2] is assigned shift[1].

Blocking Assignment

If we use blocking assignment and do the syhtheis, the synthesis tool first generate netlist for first blocking assignment and then go for the next blocking assignment. If in next blocking assignment, if previous output of the register is assigned to next, it will generate only a wire of previously assigned register.

In below Verilog code, even though all looks three different assignment but synthesis tool generate netlist for first blocking assigment which is one register, working on positive edge of clock, input d and output shift[0]. Since blocking assignment is used, for next blocking assignment, only wire is generated which is connected to shift[0]. Same is for next statement a wire is generated which is connected to shift[0].

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Comments (1)

hey in blocking assignment do we get shift in data i dont think so . we get all values same and equal to d.

Please do not focus on the module name; focus on how the netlist is generated after the synthesis.

Blocking (immediate) and Non-Blocking (deferred) Assignments in Verilog

There are Two types of Procedural Assignments in Verilog.

• Blocking Assignments
• Nonblocking Assignments

To learn more about Delay: Read  Delay in Assignment (#) in Verilog

Blocking assignments

• Blocking assignments (=) are done sequentially in the order the statements are written.
• A second assignment is not started until the preceding one is complete. i.e, it blocks all the further execution before it itself gets executed.

Non-Blocking assignments

• Nonblocking assignments (<=), which follow each other in the code, are started in parallel.
• The right hand side of nonblocking assignments is evaluated starting from the completion of the last blocking assignment or if none, the start of the procedure.
• The transfer to the left hand side is made according to the delays. An intra- assignment delay in a non-blocking statement will not delay the start of any subsequent statement blocking or non-blocking. However normal delays are cumulative and will delay the output.
• Non-blocking schedules the value to be assigned to the variables but the assignment does not take place immediately. First the rest of the block is executed and the assignment is last operation that happens for that instant of time.

To learn more about Blocking and Non_Blocking Assignments: Read Synthesis and Functioning of Blocking and Non-Blocking Assignments

The following example shows  interactions  between blocking  and non-blocking for simulation only (not for synthesis).

For Synthesis (Points to Remember):

• One must not mix “<=” or “=” in the same procedure.
• “<=” best mimics what physical flip-flops do; use it for “always @ (posedge clk..) type procedures.
• “=” best corresponds to what c/c++ code would do; use it for combinational procedures.

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Related posts:

• Synthesis and Functioning of Blocking and Non-Blocking Assignments.
• Delay in Assignment (#) in Verilog
• Ports in Verilog Module
• Module Instantiation in Verilog

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• Getting started with verilog
• Hello World
• Procedural Blocks
• Non-blocking assignments
• Simple counter
• Synthesis vs Simulation mismatch

verilog Procedural Blocks Non-blocking assignments

Fastest entity framework extensions.

A non-blocking assignment ( <= ) is used for assignment inside edge-sensitive always blocks. Within a block, the new values are not visible until the entire block has been processed. For example:

Notice the use of non-blocking ( <= ) assignments here. Since the first assignment doesn't actually take effect until after the procedural block, the second assignment does what is intended and actually swaps the two variables -- unlike in a blocking assignment ( = ) or assignments in other languages; f1 still has its original value on the right-hand-side of the second assignment in the block.

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Verification Guide

SystemVerilog NonBlocking assignment

Nonblocking assignment.

• non-blocking assignment statements execute in parallel
• In the non-blocking assignment, all the assignments will occur at the same time. (during the end of simulation timestamp)

Nonblocking assignment example

In the below example, a and b are initialized with values 10 and 15 respectively, after that b is being assigned to a (a value will become 15), and value 20 is assigned to b. After assignment values expected in a and b are 15 and 20 respectively. but these values will get assigned only after the simulation time-stamp.

Simulator Output:

Nonblocking assignment example-2

In the below example, a and b are initialized with value 10 and 15 respectively. x<=a+b and y<=a+b+x value of x is sum of a (10) and b (15). -> x=10+15=25. value of y is sum of a (10) ,b(15) and x (0) -> became at current simulation time-stamp value of x=0. new value will get assigned at the end of current time stamp, and new value will be available only after the current time-stamp). therefore y=10+15+0=25;

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verilog always@(*) nonblocking assignment

Everywhere I have read has said, do not use the <= operator inside an always@(*) block, yet my professor did on his solutions for one of our homeworks, and he works in the industry too. What is their reasoning for saying this if it can be done?

• nonblocking

• 1 if you added some example code, you would get a better response. –  Tony Cronin Commented Mar 22, 2014 at 23:50
• This has effectively been answered here: stackoverflow.com/questions/22565475/… –  Chiggs Commented Mar 23, 2014 at 11:07

3 Answers 3

The short answer is that you can always use either blocking or non-blocking assignments, in any situation, as long as you understand the implications for scheduling. If you understand the scheduling model, you can use NBAs (ie. <= , which is not an 'operator' in this context) in combinatorial processes, which is what your prof has done. Note that using NBAs in combinatorial code might potentially reduce simulation speed.

The problem is that practically nobody actually understands "the implications for scheduling", so most people use guidelines instead. The guidelines you should read for using NBAs are in this paper . Ask if you don't understand it. It's too complicated to summarise, but the paper suggests not using NBAs in combinatorial code.

These are just guidelines, and lots of (knowledgeable) people don't like them. Bear in mind that guidelines only exist because the language is poorly designed and defined. Also bear in mind that people who write guidelines tend not to appreciate this, and like to think that there are good reasons for their guidelines.

In LRM, it says

"The implicit event_expression, @*, is a convenient shorthand that eliminates these problems by adding all nets and variables that are read by the statement."

In Verilog, when you are using <= non-blocking assignments and want to refer flip-flops or latches, your always@(...) sensitive list must contains edge-triggered clocking and reset signals.

To make the syntax more explicit and clear, you should use always_ff or always_latch with your clocking and reset signals, not just always @* .

• This doesn't answer the question, and the always_ stuff is SystemVerilog, not Verilog. They're unnecessary in Verilog (and SystemVerilog) unless you're doing something that you probably shouldn't be doing. –  EML Commented Mar 24, 2014 at 10:08

Usually the usage of = is for combinational logic and <= for sequential logic.however, there are certain exceptions. one example is clock modeling, as described in Verilog Blocking Assignment . however, specifically for your question i believe Gotcha 30 (Nonblocking assignments in combinational logic) in 101 gotchas can explain it ( http://books.google.com/books?id=_VGghBpoK6cC&printsec=frontcover&dq=Verilog+and+SystemVerilog+Gotchas&hl=en&sa=X&ei=F9cvU_WhJYzdoASLoYHwBw&ved=0CCwQ6AEwAA#v=onepage&q=Verilog%20and%20SystemVerilog%20Gotchas&f=false )

• 1 I've got to say it - gotcha #30 ( always @(m,n) m <= m+n ) is nonsense. The real hardware oscillates, and the simulation oscillates, just as it should do. –  EML Commented Mar 24, 2014 at 10:05

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Verilog non-blocking assignments

Consider the following Verilog snippet:

In my textbook it says

A group of blocking assignments are evaluated in the order they appear in the code, whilst a group of nonblocking assignments are evaluated concurrently, before any of the statements on the left hand sides are updated.

So what does that mean here? Suppose c = 1100 , a = 11 and b = 01 at the beginning. The first statement will read as c = 0011 and the second as c[0] = 0 because the c in the second statement is 1100 since the assignments only take effect after the clock cycle if I understood the textbook correctly. But what is c in the end? Is it 1100 because of the last statement, or is it 0010 ? Please also explain why.

Both statements assign a value to c[0] , so even with nonblocking assignment, it is the last statement that prevails. This means that |b in the first statement is discarded, and the result will be 0010 . The first three bits come from the first statement, and the last bit comes from the second statement, all updated simultaneously.

It could be written as a single, less confusing statement:

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