Signals & Signal Assignments

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global_signal assignment

  • Stanley Mazor 2 &
  • Patricia Langstraat 2  

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This chapter discusses the use of signals for component interconnection and process communication. It contains the following sections:

• Structural Netlisting

• Process Communication

• Signal Declaration

• Entity Signal Port Declarations

• Signal Assignment in a Process

• Signal Delay

• Sequential Signal Assignment

• Simulation Cycle

• Simulation and WAIT

• Sensitivity List

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Stanley Mazor & Patricia Langstraat

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© 1993 Springer Science+Business Media New York

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Mazor, S., Langstraat, P. (1993). Signals & Signal Assignments. In: A Guide to VHDL. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-3216-3_5

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courses:system_design:vhdl_language_and_syntax:sequential_statements:variables

Fundamentals

  • Name within process declarations
  • Known only in this process
  • Immediate assignment
  • Keep the last value
  • Signal to variable
  • Variable to signal
  • Types have to match

Variables can only be defined in a process and they are only accessible within this process.

Variables and signals show a fundamentally different behavior. In a process, the last signal assignment to a signal is carried out when the process execution is suspended. Value assignments to variables, however, are carried out immediately. To distinguish between a signal and a variable assignment different symbols are used: ’⇐’ indicates a signal assignment and ’:=’ indicates a variable assignment.

Variables vs. Signals

A,B,C: integer; signal Y, Z : integer;   begin process (A,B,C) variable M, N: integer; begin M := A; N := B; Z <= M + N; M := C; Y <= M + N; end process; A,B,C: integer; signal Y, Z : integer; signal M, N : integer; begin process (A,B,C,M,N)     begin M <= A; N <= B; Z <= M + N; M <= C; Y <= M + N; end process;
  • Signal values are assigned after the process execution
  • Only the last signal assignment is carried out
  • M ⇐ A; is overwritten by M ⇐ C;
  • The 2nd adder input is connected to C

The two processes shown in the example implement different behavior as both outputs Z and Y will be set to the result of B+C when signals are used instead of variables.

Please note that the intermediate signals have to added to the sensitivity list, as they are read during process execution.

Use of Variables

  • signal to variable assignment
  • execution of algorithm
  • variable to signal assignments
  • no access to variable values outside their process
  • variables store their value until the next process call

Variables are especially suited for the implementation of algorithms. Usually, the signal values are copied into variables before the algorithm is carried out.

The result is assigned to a signal again afterwards.

Variables keep their value from one process call to the next, i.e. if a variable is read before a value has been assigned, the variable will have to show storage behavior. That means it will have to be synthesized to a latch or flip flop respectively.

Variables: Example

  • Parity calculation
  • Synthesis result:

In the example a further difference between signals and variables is shown. While a (scalar) signal can always be associated with a line, this is not valid for variables. In the example the for loop is executed four times. Each time the variable TMP describes a different line of the resulting hardware. The different lines are the outputs of the corresponding XOR gates.

Shared Variables (VHDL’93)

  • Accessible by all processes of an architecture (shared variables)
  • Can introduce non determinism

In VHDL 93, global variables are allowed.

These variables are not only visible within a process but within the entire architecture.

The problem may occur, that two processes assign a different value to a global variable at the same time. It is not clear then, which of these processes assigns the value to the variable last.

This can lead to a non deterministic behavior!

In synthesizable VHDL code global variables must not be used.

Chapters of System Design > VHDL Language and Syntax > Sequential Statements

  • Sequential Statements
  • IF Statement
  • CASE Statement
  • WAIT Statement

Chapters of System Design > VHDL Language and Syntax

  • General Issues
  • VHDL Structural Elements
  • Process Execution
  • Extended Data Types
  • Subprograms
  • Subprogram Declaration and Overloading
  • Concurrent Statements

global_signal assignment

GitHub

Variables vs. Signals in VHDL

Variables and Signals in VHDL appears to be very similar. They can both be used to hold any type of data assigned to them. The most obvious difference is that variables use the := assignment symbol whereas signals use the <= assignment symbol. However the differences are more significant than this and must be clearly understood to know when to use which one. If you need a refresher, try this page about VHDL variables .

Signals vs. Variables:

  • Variables can only be used inside processes, signals can be used inside or outside processes.
  • Any variable that is created in one process cannot be used in another process, signals can be used in multiple processes though they can only be assigned in a single process .
  • Variables need to be defined after the keyword process but before the keyword begin . Signals are defined in the architecture before the begin statement.
  • Variables are assigned using the := assignment symbol. Signals are assigned using the <= assignment symbol.
  • Variables that are assigned immediately take the value of the assignment. Signals depend on if it’s combinational or sequential code to know when the signal takes the value of the assignment.

The most important thing to understand (and the largest source of confusion) is that variables immediately take the value of their assignment, whereas signals depend on if the signal is used in combinational or sequential code . In combinational code, signals immediately take the value of their assignment. In sequential code, signals are used to create flip-flops, which inherently do not immediately take the value of their assignment. They take one clock cycle. In general, I would recommend that beginners avoid using variables. They can cause a lot of confusion and often are hard to synthesize by the tools.

The example below demonstrates how signals behave differently than variables. Notice that r_Count and v_Count appear to be the same, but they actually behave very differently.

Variables can be a bit tricky to display in simulation. If you are using Modelsim, read more about how to see your variables in Modelsim’s waveform window . Look carefully at the waveform above. Do you see how o_var_done pulses every 5th clock cycle, but o_sig_done pulses every 6th clock cycle? Using signals and variables to store data generates very different behavior . Make sure you clearly understand what you code will be generating and make sure that you simulate your code to check that behaves like you want!

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Updating global variable in signal handlers

Global variables are not updated in signal handlers unless of atomic types like sig_atomic_t . Given the following 2 conditions, can I safely edit global variables in signal handler?

  • If I define only one signal handler
  • If I use a sa_mask of struct sigaction to block all signals for the handler
  • Application is single threaded

Adding more details: I got a small global linked list keeping some info of its child process in it. Once I catch SIGCHLD (in parent process), in my signal handler I want to delete that node from the linked list. Can I perform this action in signal handler with above conditions and using some sort of pthread_mutex_trylock()?

Jay's user avatar

  • With regards to other signals or task-preemption? –  bash.d Commented Aug 14, 2013 at 12:52
  • Both. I beleive task preemption wont happen since there is only one signal handler and until this handler completes, normal flow will not resume. Please tell if any other task-preemption. –  Jay Commented Aug 14, 2013 at 12:55
  • 1 POSIX signals are not queued, so you cannot assume you'll reliably get a separate SIGCHLD for each child. (If two child processes exit at roughly the same time, then only one signal is generated.) This means that you should either reap all pending children in the signal handler, or better yet, just set a sig_atomic_t flag to your main thread, or raise a semaphore to a worker thread to do the actual reaping. –  Nominal Animal Commented Aug 15, 2013 at 17:14

2 Answers 2

Signal handlers have a problem accessing static data structures. From this, you can get corrupted data and such. If you try and call printf() within a signal handler, many times you will get strange output.

The same is for global variables unless you use atomic types.

Signal handler won't see global variable

Community's user avatar

  • Yep. Just recollected that signals can be asynchronous and signal handlers can be invoked any time. May be when the process was in mid way of updating global variable in its normal flow. Updating in signal handlers or while normal flow resumes, it will cause corruption. –  Jay Commented Aug 14, 2013 at 13:03

The type sig_atomic_t is DEFINITELY going to be updated. You can't rely on any other type to be updated outside of the context of the signal handler. It may be, and there is definitely no guarantee that it WON'T be updated. However, this comes down to handling of caches and multiple processors, asynchronous execution and other such things. If the compiler believes that a variable won't change, it may load it into a register and not ever reload it. That is not allowed for sig_atomic_t , so it "won't go wrong".

This is similar to "updating global variables in different threads", the update needs to be done under locks or using special atomic types. You can't use locks in signal handlers, because signal handlers could be called when there is some lock held!

Mats Petersson's user avatar

  • My application is single threaded. signals can be asynchronous and signal handlers can be invoked any time. May be when the process was in mid way of updating global variable in its normal flow. Updating in signal handlers or while normal flow resumes, it will cause corruption Can I use pthread_mutex_trylock() and safely edit global variables? (rather using pthread_mutex_lock() to avoid deadlock if lock was acquired by process in its normal flow ) –  Jay Commented Aug 14, 2013 at 13:15
  • You can't use any form of locking in a signal handler, since there is no telling where the code was when calling the signal handler - it may be half-way through setting some mutex (e.g. the pthread_mutex that you try to lock). Can you edit your question to explain a bit more about what you are actually trying to do, what the global variable represents, etc? –  Mats Petersson Commented Aug 14, 2013 at 13:19

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IMAGES

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COMMENTS

  1. 5.5.4.10.4. Global Signal Assignment

    Global Signal Assignment. 5.5.4.10.4. Global Signal Assignment. You can use the Global Signal assignment to control the global signal usage on a per-signal basis. For example, if a signal needs local routing, you set the Global Signal assignment to Off. 5.5.4.10.3.

  2. "set_instance_assignment -name GLOBAL_SIGNAL OFF" -> what does it do?

    2,098 Views. Hello Dmitry, A logic option that specifies whether the signal should be available throughout the device on the global routing paths. Global signals can be both pin- and logic-driven. Clock, output enable, register control, and memory control signals can be global signals. Turning on this option for a pin or a single-output logic ...

  3. Stratix10 Global Clock assignment is ignored

    12-21-2021 11:59 PM. Global Signal assignments only controls whether a signal is promoted using the specified dedicated resources or not, but does not control which or how many resources are used. To take full advantage of the routing resources in a design, make sure that the sources of clock signals (input clock pins or internally-generated ...

  4. GLOBAL_SIGNAL assignment for internal net.

    The problem is that when I synthesize my example and go to assign logic options in the Assignment Editor I can't find MyGatedClock signal in the Node Finder. I set filter to "Design Entry (all names) and use * as name and scope is set to top level but when I hit 'List' I'm presented with all ports and signals from my code bar 'MyGatedClock'.

  5. ID:16769 The global signal types are incompatible. Ensure that the

    ACTION: Ensure that the global signal types are consistent in your design, specifically that the Global Signal logic option assignments on the destination ports are the same. You can also modify the type of the existing clock buffer at the specified node to match the global signal type. Alternatively, use can you local routing instead of a ...

  6. Global Signal logic option

    A logic option that specifies whether the signal should be available throughout the device on the global routing paths. Global signals can be both pin- and logic-driven. Clock, output enable, register control, and memory control signals can be global signals. Turning on this option for a pin or a single-output logic function signal is ...

  7. Using VHDL global signals (signals declared in a package)

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  8. PDF 5 Signals & Signal Assignments

    5.6 Signal Assignment in a Process Signal assignments schedule a value at some instant in simulated time to a target previously declared as a signal object. Such an assignment defines a driver of a signal. Signal assignments are sequential within a process or concurrent outside of a process (see Chapter 6). Within a process, signal assignment ...

  9. How to assign a global clock to a pin

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    I found that if I rename GND symbol manually in schematic the Global Signal Name property has two notes - Symbol Value (name from Mentor); Block name (manually changed name) If I run my script, I'm able to change Symbol Value to new name, but not sure how to add Block Value. It seems that without Block Value Mentor change back the name to GND.

  11. Please help me How to set Global signal?

    And set the three pins as Global Signal ON and Auto Global Clock ON.But this time Quartus II said" Warning: Assignment for entity set_instance_assignment -name GLOBAL_SIGNAL ON -to USBCLK -entity A2 was ignored" and still said"Critical Warning: (High) Rule C105: Clock signal should be a global signal. (Value defined:25).

  12. courses:system_design:vhdl_language_and_syntax:sequential_statements

    Variables and signals show a fundamentally different behavior. In a process, the last signal assignment to a signal is carried out when the process execution is suspended. Value assignments to variables, however, are carried out immediately. To distinguish between a signal and a variable assignment different symbols are used: '⇐ ...

  13. ID:176321 Illegal Global Signal option assignment for Clock ...

    However, the destination nodes of a Clock Control Block require a global signal for routing and cannot have a Global Signal option assignment of OFF. ACTION: No action is required. To avoid receiving this message in the future, remove the Global Signal option assignment from the destination nodes of the specified Clock Control Block.

  14. Variables vs. Signals in VHDL

    Variables and Signals in VHDL appears to be very similar. They can both be used to hold any type of data assigned to them. The most obvious difference is that variables use the := assignment symbol whereas signals use the <= assignment symbol. However the differences are more significant than this and must be clearly understood to know when to ...

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    KrisSodroski. 2,814 3 27 39. Yep. Just recollected that signals can be asynchronous and signal handlers can be invoked any time. May be when the process was in mid way of updating global variable in its normal flow. Updating in signal handlers or while normal flow resumes, it will cause corruption. - Jay.

  16. Question about generates and global variables

    I understand I cannot have an expression call at the output of a port map, but when I use a temporary signal to assign an out to a variable I get this error: Target of signal assignment is not a signal or Illegal concurrent statement. A snip it of code I am using. Code below may not compile, I copied the code out of the file for read ability.

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  18. How do I assign a clock in my design to use specific global,...

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